CAS Latency is the shortest amount of time needed to open a memory cell. It’s the first of four Primary timings, which include Column Address Strobe (CAS), RAS to CAS Delay, Row Precharge, and Row Active Time. Memory addresses are laid out in rows and columns like a giant table, so that:
- tCL: CAS Latency is the number of clock cycles needed to access the correct column address when the correct row is already open.
- tRCD: RAS to CAS Delay is the number of clock cycles needed to open the correct row when none are open.
- tRP: Row Precharge is the number of clock cycles needed to close an incorrect row.
- tRAS: Row Active Time is the number of clock cycles needed to close an incorrect row and open the correct row.
Some of these timings accumulate. For example, if data is needed from a cell on a different row, the number of cycles it takes to open that cell (to retrieve the data) is tRAS plus tCL.
Clock cycles refer to the memory’s clock signal, which is a wave form. A signal that cycles between high and low voltage in one second has a 1Hz (one cycle per second) frequency, so that the time required for a 1000Hz clock cycle is 1/1000 of a second. By extension, the time it takes to complete a cycle at 1GHz (billion Hz) is 1ns (billionth of a second).
Because each clock cycle takes a certain period of time, lower CAS Latency corresponds to quicker response time and better performance. And because cycle time decreases in proportion to frequency, a higher frequency that uses the same number of CAS Latency cycles also corresponds to quicker response time. The relationship between cycle time and frequency means that a CAS Latency of 8 cycles at 800 MHz is only as quick as a CAS of 16 at 1600 MHz. Thus, higher frequency numbers and lower latency numbers both improve overall memory performance.