Everything We Know About Intel’s Upcoming Alder Lake-S DDR5 Platform
It’s no secret that Intel dropped the ball on 10nm conversion, as the firm withdrew most of its Cannon Lake silicon due to low yields and thermal issues. Amazingly, that was three years into the firm’s 10nm effort! No longer encumbered by problems with its own fabs, AMD used this opportunity to outsource its production to some of the world’s most proficient producers, making mainstream desktop CPUs with up to twice as many cores. Another three years on from its initial failure, Intel is nearly ready to finally bring its version of the 10nm process to a desktop IC.
With a desktop market that’s quickly running out of patience, Intel is hoping to wow buyers with an array of technologies that leapfrog everything AMD has done so far, from a rumored “Big-Bigger” hybrid core design to PCI Express 5.0 with twice the bandwidth of its competitor. Other updates include Wi-Fi 6E with optional Killer NIC control, a 2.5GbE PHY interface, and eight additional High Speed I/O connections (for a total of 38) to support additional PCIe storage on a new, PCIe 4.0-equipped southbridge. You’re looking at enough lanes to hold four PCIe 4.0 NVMe drives at full speed, one directly from the CPU, without tapping into any of the sixteen PCIe 5.0 lanes that you might want for your graphics card. And you thought this was all about DDR5…
Speaking of DDR5, we’re seeing talk of JEDEC DDR5-6400 validation announcements from assemblers/VARs in addition to upcoming XMP kits, and it is possible that Intel might loosen restrictions on single DIMM per-channel data rates. We’re told the higher data rate is not yet likely, and that there’s another side to that discussion: The memory controllers of the new Alder Lake-S CPUs aren’t that much more capable than those of the previous Rocket Lake part, and that like the Rocket Lake they’ll use “Gear 2 mode” to remain stable at high data rates. For those who forgot, Intel introduced Gear 2 mode with its 11th-gen Core series processors to force the memory controller to run at half the memory’s bus frequency, kicking in automatically at DDR4-3200 on the 11900K and DDR4-2933 on lesser processors. Gear 2 mode caused a big increase in memory latency at the controller, and many overclockers found that they could manually force Gear 1 at data rates up to (and slightly beyond) 3600. Alder Lake-S will run DDR5 memory with Gear 2 by default, and even add Gear 4 (1/4 speed) mode for super-high data rate versions. DDR4 is still an option for those who choose a motherboard thus equipped, and we wouldn’t be surprised if the CPU defaults to the lower-latency Gear 1 mode at data rates from 3200 downward.
And with that TLDR out of the way, here’s the quick list:
- Supports both DDR4 and DDR5, with standard data rates of at least DDR5-4800 compliant on four module configurations.
- Will automatically use Gear 2 or Gear 4 modes for DDR5, running the memory controller at ½ or ¼ speed, depending on data rate.
- Retains 20 CPU PCIe lanes, but 16 of those are increased to PCIe 5.0 data rates.
- Uses DMI 4.0 to connect the CPU to the PCH (chipset) at PCIe 4.0 x8 speeds.
- New PCH has four more PCIe lanes, including 12 PCIe 4.0 and 16 PCIe 3.0.
- Supports up to four USB 3.2 2×2 (20Gb/s) ports.
- New CNVio modules support Intel Wi-Fi 6E, and possibly Wi-Fi 7.
- Uses “Big-Bigger” hybrid cores to improve thread handling while retaining 125W TDP.
- Lower stack height requires new CPU cooler bracket.
While some performance enthusiast have ridiculed the idea of hybridized core architectures where some of the cores are optimized for top performance and others for efficiency, others are fully aware that some processes are far lighter than others. Whether or not the new platform is immediately successful appears contingent upon Intel’s ability to develop a scheduler that can immediately and reliably differentiate between these tasks. If all else fails, Alder Lake-S could be the stopgap measure that moves Intel a step closer to its predicted 7nm success.
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For the love of x86 Jesus… Where is the CACHE memory? Can we please abandon the “more is less” or “let’s not waste realestate for on-die memory” bullshit? Let’s be realistic who really gives a shit if we spend a few more watts and just double it.